For Analog to Digital (AD) conversion of Metal-Oxide-Semiconductor (MOS) image sensors, so-called single-slope AD conversion circuits have been used. The single-slope AD conversion circuits convert a gradually changing analog value of a reference signal voltage to a digital signal value according to information regarding a time period from when the reference signal voltage is generated to when a value relationship between the reference signal voltage and a signal voltage is changed.
Referring to FIG. 9, the following describes a structure of a conventional solid-state imaging device disclosed in Patent Literature 1. The conventional solid-state imaging device includes single-slope AD conversion circuits provided for respective columns of pixels.
As illustrated in FIG. 9, a solid-state imaging device 1001 includes a pixel array 1010 where a plurality of pixels 1003 are arrayed in rows and columns (in other words, two-dimensionally arrayed in a matrix). Each of the pixels 1003 includes a light-receiving element (an example of an electric charge generation unit) that outputs a signal corresponding to an amount of incident light. Thereby, each of the pixels 1003 outputs a signal voltage. The solid-state imaging device 1001 includes Analog Digital Converters (ADCs) each provided to a corresponding one of the columns of the pixels 1003.
More specifically, in the solid-state imaging device 1001, outside the pixel array 1010, there are provided: a drive control unit including a vertical scan circuit 1014, a timing control circuit 1020, and a horizontal scan circuit 1012; and a column processing unit 1026 including column AD circuits 1025 each provided to a corresponding one of the columns; a reference voltage generation unit 1027 that supplies a plurality of reference signal voltages Vref1 and Vref2 to the column processing unit 1026 to be used in AD conversion.
Each of the column AD circuits 1025 includes a voltage comparison unit 1252, a counter/data storage unit 1254, an AD conversion selection circuit 1253, a switch 1255, a switch 1256, and a capacitance 1257.
The drive control unit has a control circuit function of sequentially reading signals from the pixel array 1010. For example, the drive control unit includes the horizontal scan circuit (column scan circuit) 1012 that controls column addresses and column scanning; the vertical scan circuit (row scan circuit) 1014 that controls row addresses and row scanning; and the timing control circuit 1020 having a function of generating an internal clock.
Each of the pixels 1003 is connected to the vertical scan circuit 1014 via a row control line 1015 used to select a row, and also connected to the column processing unit 1026 via a column signal line 1019. Here, the row control line 1015 refers to an entire line from the vertical scan circuit 1014 to the pixels 1003.
The horizontal scan circuit 1012 has a function of a readout scan unit that reads a count value from the column processing unit 1026 to a corresponding one of horizontal signal lines (not illustrated) via a horizontal control line 1016 used to select a column.
Each of the horizontal scan circuit 1012 and the vertical scan circuit 1014 includes, for example, a decoder, and starts scanning in response to a control signal provided from the timing control circuit 1020. The vertical scan circuit 1014 selects a row in the pixel array 1010 and supplies a necessary pulse to the selected row. The horizontal scan circuit 1012 sequentially selects the column AD circuits 1025 in the column processing unit 1026 so as to provide a signal of the selected column AD circuit 1025 to a corresponding one of the horizontal signal lines (horizontal output lines). It should be noted that the horizontal signal lines are provided in number corresponding to, for example, n bits (where n is a natural number) which the column AD circuit 1025 can deal with. For example, in the case of 10 bits (n=10), ten horizontal signal lines are provided.
Furthermore, pixel signals outputted from the pixels 1003 in each column are provided to a corresponding column AD circuit 1025 in the column processing unit 1026 via a corresponding column signal line 1019. Each of the column AD circuits 1025 in the column processing unit 1026 receives analog signals of pixels 1003 in a corresponding column, and processes the received analog signals.
Here, the AD conversion performed by the column processing unit 1026 adopts a method by which analog signals provided in parallel from the columns for each row are AD-converted by the column AD circuits 1025 provided to respective columns, into digital signals in parallel for each row. In this method, a technique of single slope integration (or ramp signal comparison) AD conversion is used.
In the single slope integration AD conversion, a target analog signal is converted to a digital signal based on a time period from when the conversion starts to when the reference signal voltage Vref1 or Vref2 becomes equal to the target signal voltage. In principle, the single slope integration AD conversion is performed in the following manner. Supply of ramp reference signal voltage Vref1 and Vref2 to a comparator (voltage comparator) is started, and counting (number count) by a clock signal is also started at the same time. Then, an analog pixel signal provided via the column signal line 1019 is compared to each of the reference signal voltages Vref1 and Vref2. Until a pulse signal indicates that an analog pixel signal is equal to each of the reference signal voltages Vref1 and Vref2, the counter/data storage unit 1254 keeps counting the clock counts.